Interrupts & DMA

Polling · Interrupts · Vector Table · DMA

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How CPUs avoid wasting billions of cycles waiting on slow devices — through interrupt-driven I/O and direct memory access.

By the end, you can

Explain why polling wastes CPU cycles and describe what interrupt-driven I/O does differently.
Recite and sequence the six steps the CPU performs when a hardware interrupt arrives.
Distinguish a hardware interrupt (asynchronous, from a device) from a software interrupt/trap (synchronous, from an instruction).
Identify events that trigger a non-maskable interrupt and explain why it cannot be deferred.
Calculate the number of CPU load-store pairs required to transfer N bytes without DMA.
Describe how a DMA transfer works: what the CPU programs, what the controller does as bus master, and when the interrupt fires.
Compare burst, cycle-stealing, and transparent DMA modes and choose the right one given a system constraint.
Correct the misconception that the CPU copies every byte in a disk or network transfer.

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