CPU Deep Dive

Fetch · Decode · Execute

1:00

How the CPU fetches, decodes, and executes billions of instructions per second — including clock speed, pipelining, multi-core parallelism, and the memory hierarchy.

By the end, you can

Name the five stages of the instruction cycle and describe what happens in each.
Explain the roles of the Control Unit, ALU, and registers inside a CPU.
Calculate the number of clock cycles per second from a GHz figure, and explain why GHz alone does not determine real-world performance (instructions-per-cycle, pipeline stalls, and memory latency matter just as much).
Describe how pipelining raises throughput without reducing per-instruction latency, and explain how data, control, and structural hazards can stall the pipeline.
Distinguish true parallelism (multiple cores executing at once) from concurrency (time-slicing many tasks on one core), and give an everyday example of each.
Order the memory hierarchy from fastest to slowest, give approximate cycle counts for each level (registers ~1, L1 ~4, L2 ~12, L3 ~40, RAM ~200, disk millions), and explain why locality of reference makes caching effective.
Trace the end-to-end steps of a simple arithmetic instruction from fetch to output.

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