Lesson 043
CPU Pipelining
The Processor's Assembly Line
1:00How a processor overlaps five instruction stages like an assembly line to dramatically raise throughput — and the hazards that get in the way.
By the end, you can
- Name and describe the five classic pipeline stages in order.
- Explain why pipelining raises throughput without reducing per-instruction latency.
- Calculate the number of cycles to run N instructions in a k-stage pipeline using k + (N − 1).
- Compute and interpret the pipelining speedup relative to unpipelined execution.
- Distinguish data, control, and structural hazards and identify an example of each.
- Explain how forwarding resolves most data hazards with zero stalls, and why load-use still requires one stall.
- Describe how branch prediction and pipeline flushing handle control hazards.
- Explain why separate instruction and data caches eliminate the common structural hazard.
- Distinguish superscalar execution from out-of-order execution and state what each improves.
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