Caches & the Memory Hierarchy

Locality, cache lines & AMAT

1:00

Why memory is a pyramid of speed vs size — and how locality, cache lines, and AMAT let you write code that stays in the fast tiers.

By the end, you can

Explain why the flat-memory model is a myth and describe the memory hierarchy pyramid.
State approximate latencies for registers, L1 cache, RAM, and disk, and compare their sizes.
Distinguish temporal locality from spatial locality and give an example of each.
Explain why caches fetch whole cache lines and how this exploits spatial locality.
Categorize a miss as compulsory, capacity, or conflict given a scenario.
Compare direct-mapped, set-associative, and fully-associative placement policies.
Distinguish write-through from write-back and explain the traffic trade-off.
Compute AMAT given hit time, miss rate, and miss penalty, and explain why tiny miss rates still hurt.
Predict whether a loop pattern is cache-friendly based on row-major array layout.

Up next in Computer Architecture & Operating Systems