Advanced Computer Architecture

ILP · Out-of-Order · Speculation · SIMD · Multicore

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How modern CPUs squeeze out far more performance than a simple in-order pipeline — superscalar issue, out-of-order execution, branch speculation, SIMD, cache coherence, GPU throughput, and Amdahl's Law.

By the end, you can

Explain what superscalar and out-of-order execution mean, and why a reorder buffer is needed to restore sequential semantics.
Identify true (RAW) data dependencies versus false (WAW/WAR) dependencies, and explain how register renaming removes false ones.
Trace the 7-stage out-of-order engine pipeline (fetch, rename, dispatch, issue, execute, broadcast, retire).
Describe how branch prediction and speculation keep pipelines full, and what happens on a mispredict.
Explain why Spectre and Meltdown work — specifically why rolling back speculative registers does not undo cache side-effects.
Convert between SIMD register widths and number of float lanes (SSE: 4, AVX: 8, AVX-512: 16).
Describe all four MESI cache coherence states and trace the state transitions when cores load, share, and write a cache line.
Contrast CPU design (few complex cores, low latency) with GPU design (thousands of simple SIMT lanes, high throughput).
Apply Amdahl's Law to compute the maximum parallel speedup for a given serial fraction, and explain why the serial fraction is a hard ceiling.

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